In semiconductor processing, the formation of structures and devices generally include the sequential formation of one layer of material or composition of materials over another layer. These layers are commonly etched or doped using photolithography techniques to direct the areas where the layers are etched or doped. For example, the formation a source/drain region of a transistor may include forming a photoresist layer over the semiconductor substrate in which a source/drain region is to be formed, exposing the photoresist layer to light such that the volume of photoresist above the area where the source/drain region is to be formed is removed, and doping the semiconductor substrate using the photoresist to prevent unexposed areas from being doped. Further, a contact to the source/drain region may include depositing an insulating layer over the semiconductor substrate, forming a photoresist over the insulating layer, exposing the photoresist to light such that a volume of photoresist over the source/drain region is removed, etching the insulating layer using the photoresist as a mask, and depositing a metal.
The integrity of the devices formed using these photolithography techniques is therefore dependent upon proper alignment of features from one layer to another. In the example above, the contact must be aligned with the source/drain region. Misalignment between these layers may prevent a device from being operational.
The semiconductor processing field has developed alignment marks to allow higher precision in aligning photolithographic processes between layers. Alignment marks allow for the measurement of the placement of a wafer upon which processing has proceeded. Based on a measurement, a stepper may move or modify the position of the wafer to help enable better alignment of the photolithography processes.